Random Access Memory (RAM) can be generally classified as dynamic RAM (DRAM) or static RAM (SRAM). Since the SRAM may be more expensive (but faster) than a DRAM, an SRAM may be used as a fast small-sized external or internal cache memory device. The DRAM may be used as a general memory device that can operate at relatively slow speeds (compared to a cache memory device).
The DRAM is a volatile memory device that loses data when power is cut off. Also accumulated charges (used to store data) are reduced over time so that stored data may be lost even though power is maintained. Accordingly, it is known to periodically “refresh” the memory to maintain the stored data using a control circuit. Also, power consumption in DRAMs may be an important matter. Accordingly, it is known to reduce the amount of current to be consumed by the memory.
FIG. 1 is a block diagram of a conventional semiconductor memory device having a word line activation structure. Referring to FIG. 1, the DRAM includes a plurality of sub-memory cell arrays 40a, 40b, 40c and 40d. Each of the sub-memory cell arrays 40a, 40b, 40c and 40d includes a plurality of word lines (partially shown), a plurality of pairs of bit-lines (not shown) and a plurality of memory cells (not shown). The memory cells are positioned at intersections of the word lines and the bit lines. Sense amplifiers 50a, 50b, 50c and 50d are positioned between the sub-memory cell arrays 40a, 40b, 40c and 40d in parallel with the bit lines. The sense amplifiers 50a, 50b, 50c and 50d are shared by the adjacent sub-memory cell arrays 40a, 40b, 40c and 40d. 
Referring still to FIG. 1, on both sides of each of the sub-memory cell arrays 40a, 40b, 40c and 40d, sub-word line drivers (SWDs) 30a, 30b and 30c are positioned in parallel with the word lines. Each of the SWDs 30a, 30b and 30c selects a corresponding word line in response to a main word line enable signal WLEj output from a main word line enable signal WLE generator 24 and a sub-word line enable signal PXi output from a sub-word line enable PXI generator 22. Conjunction regions 60a, 60b and 60c are positioned between the adjacent SWDs in parallel with the bit lines.
According to FIG. 1, if a row active command is applied and PX<0> and WLE <0> are selected by address decoding of a row decoder 20, the SWD 30a and the SWD 30c are enabled and the word line corresponding to the address provided is activated. Even though not shown in FIG. 1, if a row active command is applied and PX<0> and WLE <0> are enabled by the decoding of the row decoder 20, the SWD 30a, the SWD 30b and the SWD 30c are driven and the word line WL<0> corresponding to the address provided is activated. In FIG. 1, the word line is divided into two word line segments WL<0_1> and WL<0_2>. In operation, the two word line segments are simultaneously activated by the SWD 30a and the SWD 30c respectively.
As appreciated by the present inventors, the conventional semiconductor memory receives an address associated with a row active signal decoded by the command decoder, wherein the entire word line corresponding to the entire row address provided to the row decoder is activated. A portion of a word line of the semiconductor memory is activated and the sub-memory cell array activated in accordance with the word lines does not read or write data from or to all the sub-memory cell arrays. In other words, in FIG. 1, multiple sub-word line drivers may be activated even though the command to be carried out may require fewer sub-word line drivers to be activated. For example, AND2 and AND1 may both receive the signals needed to enable their respective outputs coupled to the different word line segments. Accordingly, all of the word line segments selected by a row address may be activated even though fewer may be sufficient to carry out the requested operation, thereby possibly increasing power consumption.
It is known to reduce unnecessary power consumption by activating only specific portions of the word line segments. In some conventional methods for activating only a specific portion of the word lines, a region of sense amplifier required to read and write data is set and only word lines corresponding to the “set” sense amplifier region are activated. This approach may require an additional address input to select the corresponding sense amplifier region. For example, if the sense amplifier region is divided into two regions and the word line is divided into two, one additional address may be required to select the appropriate sense amplifier region. If the sense amplifier region is divided into four regions and the word line region is divided into four, two additional addresses may be required. Accordingly, this method may be effective in reducing current, but may require additional address inputs. The addition of an address may require the addition of another address pin to the device and another signal line so that the design of a chip is further complicated. Furthermore, an additional refresh circuit may be required to refresh each of the divided word line regions.
Word line structures are also discussed, for example, in Korean Laid Open Patent Publication Nos. 10-2002-33883, 10-2002-84893, and 10-2002-36252.